In the manufacture of integrated circuits, after the incorporation in the silicon chip of the various different conductivity regions that form its circuit components, there arises the need to interconnect these components. Generally this is done by forming over the surface of the silicon chip layers that include patterned metal layers and intermetal dielectric layers. Typically such layers also need to include vias and grooves by way of which the metal layers make connections to one another or to selected portions of the surface of the silicon chip.
As integrated circuits get more dense, it becomes particularly important to keep stray capacitance between the metal layers small. This favors the use of intermetal dielectric layers that have a low dielectric constant, such as layers of organic compositions. Various organic materials, that are free of silicon such as amorphous fluorocarbons, parylenes, and polyarylethers, are considered prime candidates for this role. Since these materials, unlike silicon oxide and silicon nitride, which have typically been used for intermetal dielectric layers, do not include silicon, they generally are etchable in oxygen plasmas. This poses problems since the use of oxygen plasmas is the method of choice for stripping the residual photoresist and anti-reflection coatings (ARC) that are in wide use in the photolithography used for patterning the various layers involved. Hence for the continued use of oxygen plasmas in such roles, it is often important to use hard masks to pattern vias and grooves in such organic intermetal dielectrics, where a "hard mask" is one that is little eroded when serving its masking function.
The present invention has particular application to dual damascene processes for providing the intermetal dielectric layers. Dual damascene processing is described in detail in an article entitled "Making the Move to Dual Damascene Processing" that appeared on pages 79-82 of Semiconductor International, August 1997, which publication is incorporated herein by reference. As is described in this paper, damascene processing involves the creation of interconnect lines by first etching a trench in a planar dielectric layer and then overfilling the trench with a first metal, such as aluminum or copper. After this filling, the metal and dielectric layers are planarized, typically by chemical mechanical polishing (CMP). Dual damascene processing involves a second metallic level in which a series of holes (vias) are etched in a dielectric layer and filled in addition to the trench. Such metal levels generally are separated by a dielectric layer, described as the intermetal dielectric (IMD). The need for two levels of metal requires the need for at least two steps in the intermetal dielectric. Typically this has been done by multiple patterning and etching of the IMD.
The main advantage of the damascene process is the elimination of the need to etch the metal layer that provides the interconnections. Another advantage is that it can eliminate the need for a dielectric gap fill. A third advantage is that it avoids some of the problems associated with lithographic overlay tolerance, making it possible to achieve higher interconnect packing density.